4 ms·

One place where LMUL makes a ton of sense is big-little hybrid designs. Your big cores can get wider execution units that can run LMUL=2 instructions natively w

One place where LMUL makes a ton of sense is big-little hybrid designs. Your big cores can get wider execution units that can run LMUL=2 instructions natively while your little cores break them up into LMUL=.5 and processes them 4x slower. This lets you avoid the issue Intel 12th gen ran into where the consumer chips lost AVX-512 capability because the little cores only supported 256 wide vectors. Also code size reduction can be pretty nice. It doesn't show up well in microbenchmarks but lowering load on the front end of your CPU is always nice. It means you get to save a little power or use the area for extra execution units.

RaisingSpear 3y ago
> Your big cores can get wider execution units that can run LMUL=2 instructions natively while your little cores break them up into LMUL=.5 and processes them 4x slower RVV spec doesn't allow LMUL to vary across cores in a hybrid design, so no, that doesn't work. RVV doesn't do anything to help with hybrid cores with differing widths. > It means you get to save a little power or use the area for extra execution units. Power, maybe, but I don't see the rest being likely. For general purpose cores, you're going to need a wide enough front end to support scalar code, which tends to have more execution units than vector.
- adgjlsfhk1 3y ago
  I'm not saying that the supported lmul varies. I'm saying that the different cores will break up the same instructions into bigger or smaller execution unit units.
  - RaisingSpear 3y ago
    There's nothing inherent with RVV or LMUL which makes this any easier/harder than other ISAs. Intel could design their little cores to break AVX-512 instructions into 4x128b parts if they felt like it, for example.
    - adgjlsfhk1 3y ago
      That's technically true, but it means that the best way of handling vector instructions on little cores is something you were going to do anyway.
      - RaisingSpear 3y ago
        Sorry, I don't quite understand you there - what is the "something" you speak of, and who does "you" refer to?

RaisingSpear 3y ago

> Your big cores can get wider execution units that can run LMUL=2 instructions natively while your little cores break them up into LMUL=.5 and processes them 4x slower RVV spec doesn't allow LMUL to vary across cores in a hybrid design, so no, that doesn't work. RVV doesn't do anything to help with hybrid cores with differing widths. > It means you get to save a little power or use the area for extra execution units. Power, maybe, but I don't see the rest being likely. For general purpose cores, you're going to need a wide enough front end to support scalar code, which tends to have more execution units than vector.

adgjlsfhk1 3y ago
I'm not saying that the supported lmul varies. I'm saying that the different cores will break up the same instructions into bigger or smaller execution unit units.
- RaisingSpear 3y ago
  There's nothing inherent with RVV or LMUL which makes this any easier/harder than other ISAs. Intel could design their little cores to break AVX-512 instructions into 4x128b parts if they felt like it, for example.
  - adgjlsfhk1 3y ago
    That's technically true, but it means that the best way of handling vector instructions on little cores is something you were going to do anyway.
    - RaisingSpear 3y ago
      Sorry, I don't quite understand you there - what is the "something" you speak of, and who does "you" refer to?