14 ms·
SiFive's 2-stage pipeline E20 (and Arm's Cortex M0+) still execute 1 instruction per clock cycle on straight line code -- they just take an extra cycle on any t
by brucehoult 3y ago
SiFive's 2-stage pipeline E20 (and Arm's Cortex M0+) still execute 1 instruction per clock cycle on straight line code -- they just take an extra cycle on any taken branch .. doesn't matter whether conditional, unconditional, call, return.
SERV takes 32 clock cycles for most instructions, 64 cycles for some such as shifts and branches.
Yes, there are some things SERV is fast enough for, but E20 is not all that much slower than 5-stage pipe plus branch prediction E31 -- E20 does 1.2 DMIPS/MHz compared to E31 1.6 (and Arm Cortex M0+ 0.95, M3/M4 1.25)