3 ms·

I wonder how good this sort of chip would be for (parallel capable) compilers. They have lots of branchy cache-missy sort of code and can often scale up to a lo

• convolvatron 3y ago
  potentially...really good? however there are lots of pitfalls. if your thread creation and teardown is expensive, then that limits the grain to which you can apply threading (Amdahl). if synchronization is expensive then you have a similar problem (that potentially gets worse with contention). one of the big problems is exactly _how_ to map threads to workloads. you don't want to leave idle resources on the ground, but its also very counterproductive to generate a massive work queue. there are also limits - memory transaction concurrency and memory bandwidth, and the costs and contention of going off chip. cache coherency, while it seems nice from a programming model perspective, can also really limit how much concurrency you can exploit. I know there are others here that can add to this list.
  • nvm0n2 3y ago
    Yes, all the usual scaling issues, of course it assumes a compiler that doesn't spend all its time contending on one big lock or sitting in cache coherency because it's doing an atomic increment of a single shared counter. But once you have the hardware it becomes reasonable to spend time fixing those issues. They're not fundamentally hard, compilers are mostly semi-functional transforms over large data structures.