3 ms·
One of the key techniques for radiation hardening is big transistor geometries. Big transistors are less susceptiple to SEU (single event upset) caused by cosmi
by dreamcompiler 3y ago
One of the key techniques for radiation hardening is big transistor geometries. Big transistors are less susceptiple to SEU (single event upset) caused by cosmic rays [0].
Unfortunately big transistors are old transistors. Modern 7 nm geometries are much too small to be rad-hard. Rad-hardness needs big 20-year-old geometries or even older. That also implies slower clock speeds.
[0] https://en.m.wikipedia.org/wiki/Single-event_upset https://en.m.wikipedia.org/wiki/Single-event_upset
- JoeAltmaier 3y agoSurely redundant transistors would also be a useful technique. E.g. have an array of transistors at the current geometry, all doing the same function. The chance of a single event upsetting them all becomes unlikely.
- dotnet00 3y agoYes, the strategy IIRC SpaceX's Dragon uses is to have 3 more modern CPUs tied together, such that they're all running the same operation and checking each other. It mitigates errors without as much of a performance penalty.