3 ms·

Reminds me of Tera, the original SMT. 128 threads per core in 1990! https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=108b3a24274af0aab079bd94ab7

• deleted 3y ago
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• yvdriess 3y ago
  Their multithreaded cores are similar design, yes. It does not do XMT's in-hardware full/empty bit memory access system though.
• pmayrgundter 3y ago
  Following the history here, DARPA also funded work in ~2005 on a project Monarch, that I saw presented at a Google tech talk back then. I believe it refers to the "butterfly" architectures of very scalable interconnects of lightweight processing units Bill Dally was working on the networking side (maybe equiv to the photonics interconnect here) and almost got it up and running at BBN (search for "monarch") http://franki66.free.fr/Principles%20and%20Practices%20of%20Interconnection%20Networks.pdf http://franki66.free.fr/Principles%20and%20Practices%20of%20... Here's some refs for the chip https://slideplayer.com/slide/7739558/ https://slideplayer.com/slide/7739558/ https://viterbischool.usc.edu/news/2007/03/monarch-system-on-a-chip-excels-in-early-testing/ https://viterbischool.usc.edu/news/2007/03/monarch-system-on... 6 main RISC processors with 96 ALUs for the lightweight IO/compute processes