My mistake - I was reading the RISC OS documentation and assumed that SWI &31 in RISC OS (not x86) was a hardware interrupt call and not something specific to R

My mistake - I was reading the RISC OS documentation and assumed that SWI &31 in RISC OS (not x86) was a hardware interrupt call and not something specific to RISC OS itself - apologies, middle of the night, brain fog!