>but i also think that if your hardware budget includes enough ram and battery to run linux it's unlikely that issues like these will be very significant Yeah,

>but i also think that if your hardware budget includes enough ram and battery to run linux it's unlikely that issues like these will be very significant Yeah, when you have that much ram, code density advantage matters less (although in L1$ it will still matter), and other factors weight more. When it's designed for realtime, then high assurance and formal verification enter the game. There, I'd argue that the complexity of the ARM ISA runs counter to the goals, and RISC-V does an order of magnitude better. >this weekend i'm prototyping a jit compiler with the objective of keeping most of my code in a bytecode form that's denser than even thumb-2 or rv32c; i anticipate about 20% better code density and about a 2-4× slowdown, with on the order of 64 clocks per instruction of compilation time. i think this should mostly eliminate the rv64c code density advantage, which i agree is pretty killer. that's not why i'm doing it, of course (i love risc-v) Seems you're having a fun weekend. I am instead playing with old hardware, and reading some 80s book on serial comms.