There are a number of RTOS’s out there now, both proprietary (e.g. VxWorks) and OSS (Zephyr) that support A-series chips with an MMU, and can operate with a sin

There are a number of RTOS’s out there now, both proprietary (e.g. VxWorks) and OSS (Zephyr) that support A-series chips with an MMU, and can operate with a single (kernel) context. They still provide bounded latencies compared to full-fat OS’s, but don’t have as much determinism as microcontrollers without page tables and caches. The cores themselves (maybe not the A35?) don’t generally work without the MMU enabled, because most ARM cores also disable the cache if the MMU is off.