> If you do not want to use one 4-bit ALU or adder, but you want to use only one single-bit adder for serial additions, that does not reduce the number of TTL c

> If you do not want to use one 4-bit ALU or adder, but you want to use only one single-bit adder for serial additions, that does not reduce the number of TTL circuits, but it increases them. The linked project implements an "1-bit ALU + sequencing + microcode" in a single PROM and just 3 TTL logic ICs (it's absolutely fair to use a PROM, because the 2900 designs all used PROMs too) Sure, it also used serial memory ICs that didn't exist in the 70s, but it wouldn't take that much TTL logic to implement the three address registers (program counter, write pointer, read pointer) and other memory support logic. Your 2900 family design also needs memory support logic too, and at least one address register. I just don't think you can beat that chip count with a microcoded AMD 2900 family design, and it's going to be significantly cheaper. In many ways it's an extremely simplified version of the exact same design, with the key parts of the ALU and Sequencer rolled into the microcode PROM chip, and every other feature discarded. Sure, the microcoded 2900 based design might result in a more capable design for not that many extra chips, but the goal here is absolute lowest IC count. ---------------------------------------- Now, if you are willing to think outside of the proposed designs in AMDs 2900 family design handbook, then maybe you improve on things by misusing chips. For example. 2910 is meant to be a 12 bit microcode sequencer, but I think it could be abused in the above design to implement the program counter plus read/write address registers in a single chip. If we also used a second one for its intended purpose, we should be able to the three TTL logic chips used for sequencing. I haven't fully thought though the design, but I think this makes it possible to do a 1bit CPU in just five chips. 8K word 16bit PROM, two AMD 2910 sequencers, one TLL chip for clock generation, and a 4K 1 bit wide SRAM chip for program/data storage. The ALU is just lookup tables in the PROM, so it should be possible to implement a two bit or three bit wide ALU by moving to a larger PROM chip and wider SRAM. Four bits might be a stretch as I want to use part of the microcode address as ALU input registers, but you could always add more PROMs and 2910s to make the whole design wider.