A710 and Zen4 both have post-decode uop caches, up to 6750 ops/core in Zen4 and 1536 ops/core in A710. (Because the uop caches must fill lines aligned to real

A710 and Zen4 both have post-decode uop caches, up to 6750 ops/core in Zen4 and 1536 ops/core in A710. (Because the uop caches must fill lines aligned to real L1 cache, utilization cannot be perfect, and x86 has a somewhat harder time to achieve full utilization, while the uop cache on arm is easier to utilize because instructions are more regular, only "losing" slots when instructions are fused.)