You mean a µop cache of size approaching that of a L1 instruction cache? The A710 has a 1536-entry µop cache. That is 3/16 of the L1 cache (counting each instr

You mean a µop cache of size approaching that of a L1 instruction cache? The A710 has a 1536-entry µop cache. That is 3/16 of the L1 cache (counting each instr as four bytes)