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The uops are similar so if x86 has a density advantage, it will be paid back during micro-op expansion. Whether this is really a win or not depends on where you
by mappu 3y ago
The uops are similar so if x86 has a density advantage, it will be paid back during micro-op expansion. Whether this is really a win or not depends on where your bottlenecks are,
- kramerger 3y agoIsn't L1 I$ at ISA level? There have been some attempts to cache microops instead but I don't think current CPUs do that.
- Findecanor 3y agoYou mean a µop cache of size approaching that of a L1 instruction cache? The A710 has a 1536-entry µop cache. That is 3/16 of the L1 cache (counting each instr as four bytes)
- Tuna-Fish 3y agoA710 and Zen4 both have post-decode uop caches, up to 6750 ops/core in Zen4 and 1536 ops/core in A710. (Because the uop caches must fill lines aligned to real L1 cache, utilization cannot be perfect, and x86 has a somewhat harder time to achieve full utilization, while the uop cache on arm is easier to utilize because instructions are more regular, only "losing" slots when instructions are fused.)