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> One key implementation decision was that the Z8000 would not make use of microcode. Microcode would have broken down the Z8000’s instructions into a series of
by MichaelZuo 3y ago
> One key implementation decision was that the Z8000 would not make use of microcode. Microcode would have broken down the Z8000’s instructions into a series of simpler instructions, hidden from the outside world, which the processor would execute. Instead, all instructions would be ‘hard-wired’ into the logic of the CPU, a more challenging approach for the designer. Shima would later discuss how much more difficult the Z8000 was to create when compared to the Z80, and how it tested the limits of the tools that he had available:
“… there are so many instructions in Z8000 it is impossible to store all of test vector for debugging in the memory of test bench anymore. Also, MOS process was getting denser and denser and also the size of the defects in masks was getting smaller. That is it was not so easy to find the fully functional die.”
This seems like a remarkable engineering decision to go entirely without microcode. Are there any comparable examples post 1979?
- deleted 3y ago[deleted]
- krylon 3y agoI was under the impression RISC architectures usually(?) don't use microcode. Or am I mistaken?
- monocasa 3y agoCorrect, true RISCs tend to not use microcode. ARM historically has, but it's also always been a bit of a RISC/CISC hybrid.
- kens 3y agoThe NEC V33 (1988) was a hardwired (not microcoded) version of the 286. The decision not to use microcode might be related to the long lawsuit between Intel and NEC over microcode. Also, as krylon points out, RISC chips generally don't use microcode.
- MichaelZuo 3y agoThanks Ken, that's pretty fascinating info. It makes me wonder if, with modern design software, a modern 64 bit CPU could be made without any microcode either.
- monocasa 3y agoDepending on what you mean by modern, there are RISC-V cores that don't use microcode, including 64-bit OoOE cores like SonicBOOM and the T-Head C920.
- dfawcus 3y agoAccording to the datasheet, which I've just looked at, it was not a '286 equivalent. Rather it added a paging mechanism whereby a 20 bit 'linear' address was mapped to a 24 bit 'physical' address. Using 1024 16k pages, so a bit like an internal LIM 4.0 scheme, but limited to 16M total rather than 24M. It has a pair of new instructions, to enter and exit the extended mapping mode, and the mappings are only changeable when not in the extended mapping mode. So a form of memory protection. See pages 20 and 21 of the following: https://datasheet.datasheetarchive.com/originals/scans/Scans-055/DSAIH000102789.pdf https://datasheet.datasheetarchive.com/originals/scans/Scans...
- kens 3y agoYou are correct.