4 ms·

I still don't know of any RISC-V implementation that supports the POPC (and related) instructions. Would like to be pointed at any. It is generally a bad idea

I still don't know of any RISC-V implementation that supports the POPC (and related) instructions. Would like to be pointed at any. It is generally a bad idea to field an instruction-set architecture that turns common, brilliant optimizations into gross pessimizations.

camel-cdr 3y ago
The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1]. You can already buy SOCs that support it, e.g. vision five 2 and star64. Interestingly the risc-v vector extension [2] has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register. Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction [3]. [0] https://github.com/riscv/riscv-bitmanip https://github.com/riscv/riscv-bitmanip [1] https://github.com/riscv/riscv-profiles https://github.com/riscv/riscv-profiles [2] https://github.com/riscv/riscv-v-spec https://github.com/riscv/riscv-v-spec [3] https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vcpop.adoc https://github.com/riscv/riscv-crypto/blob/master/doc/vector...
- angiosperm 3y ago
  Thank you. It has generally been hard to discover exactly which extensions any given implementation supports, with usually most of any comprehensive documentation in Chinese. I hope for that to change.
snvzz 3y ago
jh7110, the SoC used in the first large-scale run SBC, has popcnt as part of the related bit manipulation extensions. This is important, as it means that the first generation board to reach hordes of developers and enthusiasts is popcnt-capable.
- angiosperm 3y ago
  When I look up the jh7110, I find it has four "RV64GC" cores, which AFAICT does not call for any B-extension instructions. E.g.: https://www.cnx-software.com/2022/08/29/starfive-jh7110-risc-v-processor-specifications/ https://www.cnx-software.com/2022/08/29/starfive-jh7110-risc... https://doc-en.rvspace.org/JH7110/PDF/JH7110_Datasheet.pdf https://doc-en.rvspace.org/JH7110/PDF/JH7110_Datasheet.pdf Where do you find B-extension instructions documented? Usually we want it citing at least an RVA22U64 profile, which I do not find anywhere in these materials.
  - snvzz 3y ago
    RV64GC cores is a really vague definition of the cores. SiFive U74 21G1 is a way more precise definition. It contains many extensions to mere RV64GC. And it implements not just the 2019 version of the unprivileged spec but also a version of the privileged one. This is not implied by merely stating "RV64GC". The specification for SiFive's U74 21G1 version[0] will tell you about the details of the supported extensions. To save you the work of interpreting the document, I'll tell you it is actually Zba and Zbb, while missing the Zbc and Zbs extensions. Zbb being the one that has CPOP and related instructions, thus JH7110 has them. 0. https://starfivetech.com/uploads/u74_core_complex_manual_21G1.pdf https://starfivetech.com/uploads/u74_core_complex_manual_21G...

camel-cdr 3y ago

The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1]. You can already buy SOCs that support it, e.g. vision five 2 and star64. Interestingly the risc-v vector extension [2] has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register. Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction [3]. [0] https://github.com/riscv/riscv-bitmanip https://github.com/riscv/riscv-bitmanip [1] https://github.com/riscv/riscv-profiles https://github.com/riscv/riscv-profiles [2] https://github.com/riscv/riscv-v-spec https://github.com/riscv/riscv-v-spec [3] https://github.com/riscv/riscv-crypto/blob/master/doc/vector/insns/vcpop.adoc https://github.com/riscv/riscv-crypto/blob/master/doc/vector...

angiosperm 3y ago
Thank you. It has generally been hard to discover exactly which extensions any given implementation supports, with usually most of any comprehensive documentation in Chinese. I hope for that to change.

snvzz 3y ago

jh7110, the SoC used in the first large-scale run SBC, has popcnt as part of the related bit manipulation extensions. This is important, as it means that the first generation board to reach hordes of developers and enthusiasts is popcnt-capable.

angiosperm 3y ago
When I look up the jh7110, I find it has four "RV64GC" cores, which AFAICT does not call for any B-extension instructions. E.g.: https://www.cnx-software.com/2022/08/29/starfive-jh7110-risc-v-processor-specifications/ https://www.cnx-software.com/2022/08/29/starfive-jh7110-risc... https://doc-en.rvspace.org/JH7110/PDF/JH7110_Datasheet.pdf https://doc-en.rvspace.org/JH7110/PDF/JH7110_Datasheet.pdf Where do you find B-extension instructions documented? Usually we want it citing at least an RVA22U64 profile, which I do not find anywhere in these materials.
- snvzz 3y ago
  RV64GC cores is a really vague definition of the cores. SiFive U74 21G1 is a way more precise definition. It contains many extensions to mere RV64GC. And it implements not just the 2019 version of the unprivileged spec but also a version of the privileged one. This is not implied by merely stating "RV64GC". The specification for SiFive's U74 21G1 version[0] will tell you about the details of the supported extensions. To save you the work of interpreting the document, I'll tell you it is actually Zba and Zbb, while missing the Zbc and Zbs extensions. Zbb being the one that has CPOP and related instructions, thus JH7110 has them. 0. https://starfivetech.com/uploads/u74_core_complex_manual_21G1.pdf https://starfivetech.com/uploads/u74_core_complex_manual_21G...