2 ms·

Thanks, that's very interesting and I've updated the footnote. I looked at the CDC 6600 manual and it works pretty much like you say. If you change an address r

• adrian_b 3y ago
  > I haven't come across an instruction set other than Datapoint that treated register and memory accesses identically. (If you know of exceptions, please let me know.) The DEC PDP-11 was launched in 1970, slightly earlier than Datapoint 2200. While DEC PDP-11 also had additional addressing modes, its two most simple addressing modes, register direct and register indirect correspond exactly with the addressing modes of Datapoint 2200. The only difference is how they were encoded. Because PDP-11 had longer instructions, they could afford separate bits for encoding the addressing mode. So 3 bits encoded the 8 registers and a separate bit encoded whether the register is used as data (register direct) or as the address of data from memory (register indirect). Datapoint 2200 needed shorter instructions, so they have dispensed with the bit needed for encoding the addressing mode, by using only 7 registers, so that the unused register number could be used to encode the register indirect addressing mode, where the register holding the address had to be implicit, as no other bits were available to specify it. So what is special about the addressing modes of Datapoint 2200 is this encoding trick, which saves 1 bit of the instruction encoding with the price of allowing only one of the general-purpose registers to be used for memory addressing, while the addressing modes themselves are not new. This encoding trick, where it is avoided to have additional bits for encoding addressing modes, by reserving some register numbers to encode those addressing modes, has been reused repeatedly by Intel when defining the 8086 and 80386 ISAs and by AMD when defining the 64-bit extension. For instance, there are no instruction bits to encode addressing modes where the address is computed by adding a base register and an index register. Instead of that, the SP register cannot be used in the basic encoding for memory operands, so using the SP register number denotes that the address is computed by adding a base register and an index register, where those registers are specified by an extra SIB byte. There are a few other cases where some registers cannot be used with certain addressing modes, but when they appear in the instruction those register numbers mean that the operand must be accessed with some different addressing mode, like memory relative to the instruction pointer or memory absolute.
  • rep_lodsb 3y ago
    In PDP-11 terms, the Datapoint 2200 only had these "address modes" ( https://en.wikipedia.org/wiki/PDP-11_architecture#General_register_addressing_modes https://en.wikipedia.org/wiki/PDP-11_architecture#General_re... ): - register - register deferred via HL - autoincrement via PC (immediate operands) No registers other than HL and PC could be output to the address bus at all. The 8080 was much more flexible, but the instructions it added weren't orthogonal, so I would say it's not at all comparable to the PDP-11 addressing modes.