To add to this, the amount of speculation modern CPUs do is insane. In the "theLoop" example, say the first load misses L1 and L2 cache and takes needs 40 cycl

To add to this, the amount of speculation modern CPUs do is insane. In the "theLoop" example, say the first load misses L1 and L2 cache and takes needs 40 cycles to load. AMD's Zen 4 has enough resources to issue about 64 iterations of "theLoop:" all before that first load needs to complete. With the micro op cache, it can probably issue those 64 loop iterations in about 35 cycles. Zen 4 has enough resources to start all 64 loads early, so they run in parallel. Who cares if there is a branch mispredict and it you actually needed to do only 16 iterations of "theLoop"? In this example, the loop length isn't dependant on any of the loads so the CPU can actually finish executing the "add ecx, 4; cmp max; jnz theLoop;" instructions of the first 16 iterations of the "theLoop". And then detect the mispredict, flush the pipeline and load the correct branch location, all before the 40 cycles it takes for that first load to complete. ------ It's just absolutely insane. No short pipeline without a branch predictor could possibly compete.