Looks really cool and props for fixing a huge amount of spaghetti code. Now, I wonder if I can make a 3d rasterizer on a FPGA and run the CPU side on a RISC-V.

Looks really cool and props for fixing a huge amount of spaghetti code. Now, I wonder if I can make a 3d rasterizer on a FPGA and run the CPU side on a RISC-V... If anyone else is intrigued by this let me know.