4 ms·

I don't get why the base ISA didn't include any atomic instructions. It's an annoying omission when even tiny embedded devices often have more than one core ava

I don't get why the base ISA didn't include any atomic instructions. It's an annoying omission when even tiny embedded devices often have more than one core available. And single-core designs could just implement them as no-op, the silicon cost is miniscule.

brucehoult 3y ago
You can't implement AMOs as no-op! That code will fail horribly! You need (in a simple core [1]) a very un-RISC read/modify/write sequencer with bus lock. That's not cheap in silicon. Or trap and emulate using LR (which could be NOP) and SC (which could be a plain store) and a few other instructions. That's not fast. If you have that tiny embedded device with more than one core then you implement RV32IA properly, simple. And if you have a single core and no interrupts or DMA then implement RV32I and save a good bit of silicon. [1] big designs don't implement AMOs in the CPU core, but out in the peripherals, RAM controller, or cache controller. As far as the CPU core is concerned an AMO is a memory read that sends extra data (a constant and an operation code) out with the memory address.