This is how process nodes have always been discussed. 3nm is the smallest feature size. That said, no, most devices that are digital logic DO scale proportiona

This is how process nodes have always been discussed. 3nm is the smallest feature size. That said, no, most devices that are digital logic DO scale proportionally. And the A17 series, almost everything is digital logic, so I expect it will either be substantially smaller or more performant, or likely both. TSMC claims the following (vs. 5nm): * 25-30% power reduction (for same logic) * 10-15% performance increase (for same logic) * 1.7x reduction in area (for same logic) (i.e., -42% size)