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You might check out what the Precursor open source phone project is up to [0], they tout a compile-it-yourself RISCV cpu running on a Xilinx Spartan 7 There's

You might check out what the Precursor open source phone project is up to [0], they tout a compile-it-yourself RISCV cpu running on a Xilinx Spartan 7 There's also a FPGA implementation of the 6502 CPU running at 100Mhz, that's on a Spartan 6 [1] I have some overlapping goals as you but plan to start with Ben Eater's 8 bit machine and NAND to Tetris. I'm curious about ternary logic - true false and maybe - like charlieplexing. I think Konrad Zuse had built something like this. Move onto designing an instruction set from there, how much can I keep it as an analogue dataflow computer instead of a stepwise serial instruction machine. I heard someone say the ENIAC was a parallel machine before von nuemann ruined it :) [0] https://www.crowdsupply.com/sutajio-kosagi/precursor https://www.crowdsupply.com/sutajio-kosagi/precursor [1] https://hackaday.com/2021/10/15/heres-a-100-mhz-pin-compatible-6502-replacement/ https://hackaday.com/2021/10/15/heres-a-100-mhz-pin-compatib...

brucehoult 3y ago
> There's also a FPGA implementation of the 6502 CPU running at 100Mhz, that's on a Spartan 6 There are plenty of free RISC-V soft cores that will run at 100 MHz on an FPGA, and that's at 1 instruction per cycle, not the 2-6 cycles per instruction that 6502 takes. Also a 32 or 64 bit RISC instruction does a lot more useful work than a 6502 instruction e.g. `add Rd, Rs1, Rs2` is one instruction and one clock cycle vs 13 instructions and 38 clock cycles for a 6502 to add two 32 bit numbers at fixed locations in Zero Page (virtual registers, if you like).