22 ms·

This is a great overview of the origin of the RISC-V project and I particularly like the history of instructions which tracks back to previous instructions that

This is a great overview of the origin of the RISC-V project and I particularly like the history of instructions which tracks back to previous instructions that were "kind of" like the current instruction. I suspect this particular set of articles are assisting the RISC-V folks hold at bay the various patent lawsuits they are clearly being threatened with. One of the worst things about technology was that so many people focused on "If we own the road, we can charge EVERYONE a toll and get rich!" and so, so many, business plans were built around gaining exclusive control over key facets of technology. The idea that there could be an instruction set architecture (ISA) and related silicon implementations that anyone could use for free, is an existential threat to those who live on the margin generated by the licensing of their ISAs. If anything can derail ARM's growing influence, it will be this. The winners will be people like Apple with the resources to have their own chips fabbed with their own extensions and put into their own products which can run rings around people trying to use "generic" processors to do the same thing. Could signal a coming resurgence in demand for "computer architects" (old skool type :-))

brucehoult 3y ago
I don't know whether anyone has ever really threatened a patent lawsuit over the ISA, but it definitely does seem to be a good idea to document the origins of instructions, and that they are either so well known and obvious that they can't be patented, or else that they were patented and the patent has expired. Another protection is that the membership application for RISC-V International includes certification that RISC-V does not infringe on the applicant's own patents. With companies such as Intel, AMD, IBM, Marvell, Microchip, MIPS, nVIDIA, NXP, Qualcomm, Renesas, Samsung, Siemens, Sony, STM, Texas Instruments being members that covers a lot of ground. The base ISA (up to RV32GC, RV64GC) very deliberately breaks no new ground. It's just smoother, with known potholes filled in. Many of the optional extensions do break some new ground. The V extension has some unique features, though the basics are inspired by the Cray-1. RVWMO is based on experience gained with ARM and DEC Alpha memory ordering models, but fixing the problems -- and was actually designed by a world-wide group of academic and industry experts. Both of these are examples of something that simply would not be done as well by a small group of people inside a single company, working to a deadline.
- _chris_ 3y ago
  I believe early on there was a change to a pre-AUIPC instruction due to potential infringement fears (for PC-relative indexing); but everything else was understood to be following well-worn paths.
  - brucehoult 3y ago
    Interesting. I hadn't heard that, but then I was a late-comer in 2016 with the user ISA already in its current form. I have some vague memory of having seen something about RISC-V a few years earlier than that, and glancing at the ISA, and not being impressed. But by the time the HiFive1 came it all looked pretty great to me. Not perfect — `SLT[I][U]` should produce 0 or -1 not 0 or 1, for example — but pretty darn good. The C extension also made it vastly more attractive as a practical ISA, and that was a late-comer (even if always "planned" and already mentioned as being developed in the May 2011 spec). Looking at the May 2011 spec (https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-...) there is `RDNPC Rd` which simply loads next PC into Rd. So that's 4 bytes different to modern `AUIPC Rd,0`, and functionally identical (other than return address predictor SNAFU) to modern `JAL Rd,.+4` or 2011 `JAL .+4` (only `x1` supported). So 32 bit PC-relative addressing needed `RDNPC;LUI;ADD` and then `JALR`/load/store vs modern just `AUIPC` before the main instruction. If there was something before `RDNPC` then it much have been very short-lived! There is allegedly an earlier RISC-V design here... https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-riscv-v2-vcs-dc-v092010a.pdf https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-ris... ... but I get "You don't have permission to access this resource." There is an updated 2011 version which appears to conform to the May 2011 spec. The instruction listing omits load/store byte/half and there is no relative addressing support at all (except `JAL 4`) but that is probably just simplification for a hardware design class. https://inst.eecs.berkeley.edu/~cs250/fa11/handouts/lab2-riscv-v2-vcs-dc.pdf https://inst.eecs.berkeley.edu/~cs250/fa11/handouts/lab2-ris... Chris, do you have access to that fa10 version?
    - _chris_ 3y ago
      I also get a permission error: but I think this (https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-riscv-v2-vcs-dc.pdf https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-ris...) is the same file, and functionally the same as the fa11 version? I think RDNPC is what I was thinking of, but I can't at all remember what was perceived as "risky" about it. I may be overblowing something from memory. AUIPC is better anyways.
peoplearepeople 3y ago
> various patent lawsuits they are clearly being threatened with. Do you have a link we could read about this?

brucehoult 3y ago

I don't know whether anyone has ever really threatened a patent lawsuit over the ISA, but it definitely does seem to be a good idea to document the origins of instructions, and that they are either so well known and obvious that they can't be patented, or else that they were patented and the patent has expired. Another protection is that the membership application for RISC-V International includes certification that RISC-V does not infringe on the applicant's own patents. With companies such as Intel, AMD, IBM, Marvell, Microchip, MIPS, nVIDIA, NXP, Qualcomm, Renesas, Samsung, Siemens, Sony, STM, Texas Instruments being members that covers a lot of ground. The base ISA (up to RV32GC, RV64GC) very deliberately breaks no new ground. It's just smoother, with known potholes filled in. Many of the optional extensions do break some new ground. The V extension has some unique features, though the basics are inspired by the Cray-1. RVWMO is based on experience gained with ARM and DEC Alpha memory ordering models, but fixing the problems -- and was actually designed by a world-wide group of academic and industry experts. Both of these are examples of something that simply would not be done as well by a small group of people inside a single company, working to a deadline.

_chris_ 3y ago
I believe early on there was a change to a pre-AUIPC instruction due to potential infringement fears (for PC-relative indexing); but everything else was understood to be following well-worn paths.
- brucehoult 3y ago
  Interesting. I hadn't heard that, but then I was a late-comer in 2016 with the user ISA already in its current form. I have some vague memory of having seen something about RISC-V a few years earlier than that, and glancing at the ISA, and not being impressed. But by the time the HiFive1 came it all looked pretty great to me. Not perfect — `SLT[I][U]` should produce 0 or -1 not 0 or 1, for example — but pretty darn good. The C extension also made it vastly more attractive as a practical ISA, and that was a late-comer (even if always "planned" and already mentioned as being developed in the May 2011 spec). Looking at the May 2011 spec (https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-...) there is `RDNPC Rd` which simply loads next PC into Rd. So that's 4 bytes different to modern `AUIPC Rd,0`, and functionally identical (other than return address predictor SNAFU) to modern `JAL Rd,.+4` or 2011 `JAL .+4` (only `x1` supported). So 32 bit PC-relative addressing needed `RDNPC;LUI;ADD` and then `JALR`/load/store vs modern just `AUIPC` before the main instruction. If there was something before `RDNPC` then it much have been very short-lived! There is allegedly an earlier RISC-V design here... https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-riscv-v2-vcs-dc-v092010a.pdf https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-ris... ... but I get "You don't have permission to access this resource." There is an updated 2011 version which appears to conform to the May 2011 spec. The instruction listing omits load/store byte/half and there is no relative addressing support at all (except `JAL 4`) but that is probably just simplification for a hardware design class. https://inst.eecs.berkeley.edu/~cs250/fa11/handouts/lab2-riscv-v2-vcs-dc.pdf https://inst.eecs.berkeley.edu/~cs250/fa11/handouts/lab2-ris... Chris, do you have access to that fa10 version?
  - _chris_ 3y ago
    I also get a permission error: but I think this (https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-riscv-v2-vcs-dc.pdf https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-ris...) is the same file, and functionally the same as the fa11 version? I think RDNPC is what I was thinking of, but I can't at all remember what was perceived as "risky" about it. I may be overblowing something from memory. AUIPC is better anyways.

peoplearepeople 3y ago

> various patent lawsuits they are clearly being threatened with. Do you have a link we could read about this?