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Once RISC-V gains market share, Intel and ARM will gradually react, lowering fees and opening their platforms proportionately, if needed. They will try to block

by aborsy 3y ago

Once RISC-V gains market share, Intel and ARM will gradually react, lowering fees and opening their platforms proportionately, if needed. They will try to block the addition of value and market capture.

eunos 3y ago
In that case the main strength of RISC-V would be Chinese companies since it is theoretically sanction resistant.
- deleted 3y ago
  [deleted]
dkjaudyeqooe 3y ago
If that happens it's a win for everyone, but unlikely in practice, given their business models. Don't see how they can block RISC-V. But an additional advantage for RISC-V is that it's a clean slate specification and very simple at its core, and that enables a lot more use cases that would otherwise be impossible due to legacy cruft.
- hashtag-til 3y ago
  Blocking won’t happen, but remember theses companies also detain a massive patent portifolio which is hard not to break while implementing similar techniques. Despite personally I really wish it was different, there is a lot of fragmentation already in RISC-V and I feel it only tends to grow given managers will always push to create some internal secret sauce.
- RetroTechie 3y ago
  What I like about RISC-V is that it's not just open for the sake of being open, but actually a well-designed architecture. Practical & effective from embedded to enterprise & beyond. For example, modularity: most other ISAs have had heaps of extensions bolted onto the ISA over time, in order to produce fast CPU cores. Things like MMX, SSEx, AVX, ARM's Thumb, Neon, etc etc. So if (for example) you want x86 core with some form of AVX, you get at least a 64 bit, 2-core cpu with SSEx, single & double precision floating point, a long list of addressing modes, support for i386 software/memory models, the works. If you want a 'minimal' core, you're looking at ancient 386 or 486, and neither AMD or Intel will bake those for you. Over in the RISC-V camp, a vendor can take a minimal core, add only those extensions needed for a System-on-Chip's intended uses, bring that to a foundry, and have software toolchain in place the day silicon is taped out. Instruction encoding is mostly (entirely?) the same between 32-bit and 64-bit versions. 64-bit simply having wider registers. Compressed "Thumb" instructions translate 1:1 to instructions with the standard 32-bit encoding. Bit fields encoding source & destination registers are always in the same place. Sign extension is trivial. No myriad of obsolete memory models. Etc, etc, as I said: well designed architecture. All these goodies enable efficient / small / cheap hardware, and relatively easy software support.

by aborsy 3y ago

eunos 3y ago

In that case the main strength of RISC-V would be Chinese companies since it is theoretically sanction resistant.

deleted 3y ago
[deleted]

dkjaudyeqooe 3y ago

If that happens it's a win for everyone, but unlikely in practice, given their business models. Don't see how they can block RISC-V. But an additional advantage for RISC-V is that it's a clean slate specification and very simple at its core, and that enables a lot more use cases that would otherwise be impossible due to legacy cruft.

hashtag-til 3y ago
Blocking won’t happen, but remember theses companies also detain a massive patent portifolio which is hard not to break while implementing similar techniques. Despite personally I really wish it was different, there is a lot of fragmentation already in RISC-V and I feel it only tends to grow given managers will always push to create some internal secret sauce.
RetroTechie 3y ago
What I like about RISC-V is that it's not just open for the sake of being open, but actually a well-designed architecture. Practical & effective from embedded to enterprise & beyond. For example, modularity: most other ISAs have had heaps of extensions bolted onto the ISA over time, in order to produce fast CPU cores. Things like MMX, SSEx, AVX, ARM's Thumb, Neon, etc etc. So if (for example) you want x86 core with some form of AVX, you get at least a 64 bit, 2-core cpu with SSEx, single & double precision floating point, a long list of addressing modes, support for i386 software/memory models, the works. If you want a 'minimal' core, you're looking at ancient 386 or 486, and neither AMD or Intel will bake those for you. Over in the RISC-V camp, a vendor can take a minimal core, add only those extensions needed for a System-on-Chip's intended uses, bring that to a foundry, and have software toolchain in place the day silicon is taped out. Instruction encoding is mostly (entirely?) the same between 32-bit and 64-bit versions. 64-bit simply having wider registers. Compressed "Thumb" instructions translate 1:1 to instructions with the standard 32-bit encoding. Bit fields encoding source & destination registers are always in the same place. Sign extension is trivial. No myriad of obsolete memory models. Etc, etc, as I said: well designed architecture. All these goodies enable efficient / small / cheap hardware, and relatively easy software support.