4 ms·
On an FPGA, it will infer a dual-ported BRAM memory just fine. On ASIC, it will generate a flip-flop array, which is good enough for many CPUs. E.g. in this ph
by tverbeure 3y ago
On an FPGA, it will infer a dual-ported BRAM memory just fine. On ASIC, it will generate a flip-flop array, which is good enough for many CPUs.
E.g. in this physical layout of a Swerv RISC-V CPU, the ARF section is the register file, built out of flip-flops: https://tomverbeure.github.io/2019/03/13/SweRV.html#swerv-physical-design https://tomverbeure.github.io/2019/03/13/SweRV.html#swerv-ph....
- alain94040 3y agoAlso, the read ports are asynchronous, which is bad: assign rv1 = registers[rs1]; assign rv2 = registers[rs2];