4 ms·
Correct. The code shown is only good enough for RTL simulation. It won't help actually generate a chip with multiple read and write ports to a register file.
by alain94040 3y ago
Correct. The code shown is only good enough for RTL simulation. It won't help actually generate a chip with multiple read and write ports to a register file.
- therealcamino 3y agoThat code is synthesizeable and will work fine in an ASIC flow.
- tverbeure 3y agoOn an FPGA, it will infer a dual-ported BRAM memory just fine. On ASIC, it will generate a flip-flop array, which is good enough for many CPUs. E.g. in this physical layout of a Swerv RISC-V CPU, the ARF section is the register file, built out of flip-flops: https://tomverbeure.github.io/2019/03/13/SweRV.html#swerv-physical-design https://tomverbeure.github.io/2019/03/13/SweRV.html#swerv-ph....
- alain94040 3y agoAlso, the read ports are asynchronous, which is bad: assign rv1 = registers[rs1]; assign rv2 = registers[rs2];