3 ms·
Quick question: under specs for the M0+ where they say, >Enhanced Instructions >Hardware single-cycle (32x32) multiply option Does that mean their hardware c
by zxcvvcxz 15y ago
Quick question: under specs for the M0+ where they say,
>Enhanced Instructions
>Hardware single-cycle (32x32) multiply option
Does that mean their hardware can multiply 32-bit by 32-bit
numbers in a single clock cycle?? I took a computer organization course where I implemented a simple hardware multiplier and it took a lot more cycles than that, so I was curious.
- abecedarius 15y agoProbably means throughput, not latency.
- omgtehlion 15y agoYou can create HW multiplier using only NOR+AND elements. It will consume a lot of silicon, but will work fast enough. BTW, most FPGAs have HW multiplier prebuilt block, because you will loose lots of flip-flops or LUTs (or both) implementing one yourself.