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Is the RTL autogenerated from the chip images? I looked at one file 68k.v and the variable names remind me of a decompiler.
by tails4e 3y ago
Is the RTL autogenerated from the chip images? I looked at one file 68k.v and the variable names remind me of a decompiler.
- qingcharles 3y agoI wondered the same thing. Otherwise that is a lot of code to write. The type of code that will cook your brain very quickly.
- lprib 3y agoIt's probably hand written but they didn't reverse engineer the purpose of each wire, only the netlist. Some of them are labeled, eg `irdbus_normal`.
- jareklupinski 3y agoguessing since the 68k and z80 cores are not specific to the genesis, they may have used another implementation (maybe https://github.com/nukeykt/Nuked-MD https://github.com/nukeykt/Nuked-MD ?) the genesis "specific" ym* cores look a lot more "authored"; commit history shows more activity around those files too but thats just a guess... something that can generate verilog from chip images would be pretty cool...
- junon 3y agoThere are assistant tools for reversing die shots, by the way. Semi-automatic, not sure if we've gotten to the point of fully automatic yet.
- rbanffy 3y agoI can’t wait to see AI applied to reverse engineering of decapped chips. Do we have tools for exposing specific layers instead of 2D images? It would, perhaps, be interesting to go with diagonal slices as we grind the chip and, aided by exaggerated vertical features, capture the full depth on a single pass.
- retro_guy 3y agoIf you are interested in more than 2D images, you might find this article interesting. - The X-Ray Tech That Reveals Chip Designs: https://spectrum.ieee.org/chip-x-ray https://spectrum.ieee.org/chip-x-ray