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Star64 JH7110 and NuttX RTOS: RISC-V PLIC Interrupts and Serial I/O

• johndoe0815 3y ago
  The spurious UART interrupts mentioned in the article are probably related to a "feature" of the DesignWare UART component used in the JH7110 SoC. When trying to write the UART's LCR (line control register) when the UART is busy, a BUSY interrupt is generated. If this is not handled, the UART will continue to generate an interrupt storm. The Allwinner D1 RISC V SoC (and several other ARM-based Allwinner chip) also uses the DesignWare UART and suffers from the same problem. See the Linux driver source for a workaround: https://elixir.bootlin.com/linux/latest/source/drivers/tty/serial/8250/8250_dw.c https://elixir.bootlin.com/linux/latest/source/drivers/tty/s...
  • lupyuen 3y ago
    Thank you so much! I'll check it out.
    • lupyuen 3y ago
      Update: We fixed the Spurious UART Interrupts by waiting for UART to be not busy before setting the Line Control Register: https://github.com/lupyuen2/wip-pinephone-nuttx/pull/36/files#diff-f208234edbfb636de240a0fef1c85f9cecb37876d5bc91ffb759f70a1e96b1d1 https://github.com/lupyuen2/wip-pinephone-nuttx/pull/36/file... I'm sorry that Codeberg is having problems, here's the backup link for the article: https://lupyuen.github.io/articles/plic https://lupyuen.github.io/articles/plic