5 ms·

> CPU heat output is limited by the resistance of the semiconductors. This is not true anymore. At leading edge process nodes (i.e., smaller conductor pitch),

> CPU heat output is limited by the resistance of the semiconductors. This is not true anymore. At leading edge process nodes (i.e., smaller conductor pitch), the bulk resistivity of copper changes dramatically because it is increasingly dominated by ballistic electron scattering on the interfaces and grain boundaries: surface area has decreased as a fraction of volume and the average grain size has shrunk to fit inside the interconnect lines. Alternative metals like Cobalt and Ruthenium have been proposed and to some extent used in production as an alternative to Cu for the low interconnect layers, but they just arrest the trend -- the fact is that the interconnect resistance is much higher than it used to be. It's also why a lot of the big players like TSMC and Intel are investing heavily in backside power delivery. Here is an accessible article on the topic: https://www.fabricatedknowledge.com/p/backside-power-delivery-and-bold https://www.fabricatedknowledge.com/p/backside-power-deliver... (Also: high-voltage DC power is commonly used for long-range transmission and does not have coupling issues)

Taniwha 3y ago
Yes RC wire delays have becoming more important than gate capacitance for a couple of decades now - if R goes to 0 RC delays do too
- whatshisface 3y ago
  I guess the next limiting factor would be LC delays.
throwawaylinux 3y ago
No it pretty much is true, well it's the power draw from switching transistors and from leakage losses. Resistance in the metal wires is not so much a problem for power as it is for signal propagation delay. That is the biggest problem with R skyrocketing in M0/1. And backside power delivery is to relieve congestion in the interconnects. That's typically one of the limiting factors in complex logic designs now, transistor densities of under 70% aren't uncommon. That's what "Removing the power signal and signal line to just a signal line would free up space for more transistors." line is about in the link. Power delivery losses aren't nothing, but they aren't a big fraction of energy in today's CPUs. Eliminating most wire delay would be a huge benefit though, and could be a pretty big revolution. Not just within the core or on the die. You're still going to have to switch those transistors and burn current on leakage though, so no cold CPUs just yet.

Taniwha 3y ago

Yes RC wire delays have becoming more important than gate capacitance for a couple of decades now - if R goes to 0 RC delays do too

whatshisface 3y ago
I guess the next limiting factor would be LC delays.

throwawaylinux 3y ago

No it pretty much is true, well it's the power draw from switching transistors and from leakage losses. Resistance in the metal wires is not so much a problem for power as it is for signal propagation delay. That is the biggest problem with R skyrocketing in M0/1. And backside power delivery is to relieve congestion in the interconnects. That's typically one of the limiting factors in complex logic designs now, transistor densities of under 70% aren't uncommon. That's what "Removing the power signal and signal line to just a signal line would free up space for more transistors." line is about in the link. Power delivery losses aren't nothing, but they aren't a big fraction of energy in today's CPUs. Eliminating most wire delay would be a huge benefit though, and could be a pretty big revolution. Not just within the core or on the die. You're still going to have to switch those transistors and burn current on leakage though, so no cold CPUs just yet.