Also for this example, it is not unusual, especially for RISC ISAs, to have to or for it to be optimal to count down rather than how we’re taught in CS/EE/CE to

Also for this example, it is not unusual, especially for RISC ISAs, to have to or for it to be optimal to count down rather than how we’re taught in CS/EE/CE to count up in loops. RISC machines can often do several interesting things with zero’d registers or flags or conditions.