The memory wall arrived decades ago. That's why caches were invented (which don't solve the problem, just soften the blow). One approach would be to snip RAM i

The memory wall arrived decades ago. That's why caches were invented (which don't solve the problem, just soften the blow). One approach would be to snip RAM in as many pieces as you have cores, and attach each piece locally to a CPU core. Say eg. 1k cores each with 1/1000th of total RAM, accessible at L1 cache like speeds. Giving you crazy-high (combined) memory bandwidth. I know, there exist some IC's that actually do this. Problem is such a setup is not suitable for all types of computation. For data structures that require individual cores to access other cores' local RAM, you still need some communication protocol (+ latency, bringing you back to square 1). And we haven't quite figured out how to program such a beast in software developer-friendly way. Hence the usual approach of "all RAM in one pile, connected via a fat pipe to a heap of CPU cores".