> do the tests really cover all of the non-redundant transistors, which I assume are a substantial portion of them? In the limit, yes! "Design for test" (DFT)

> do the tests really cover all of the non-redundant transistors, which I assume are a substantial portion of them? In the limit, yes! "Design for test" (DFT) tooling inserts extra logic beneath the RTL netlist, which allows the chip to be put in a test mode where each flop can be driven or read as a giant shift register. Automated tooling designs test patterns to clock into these registers such that every gate in the design is verified. For large chips test patterns may be multiple gigabytes (though highly compressible). Of course, this is "in the limit" and frequently (density, routing, frequency, etc) there are reasons where DFT engineers would choose to omit DFT inputs. In those cases more involved tests are needed to exhaustively verify those regions.