Weaker => more freedom to reorder => issue loads sooner => higher IPC/perf. Really that simple. You can get some of this with speculation and later checking,

Weaker => more freedom to reorder => issue loads sooner => higher IPC/perf. Really that simple. You can get some of this with speculation and later checking, but that has its own costs and limitation. People feel _very_ strongly about these topics. RISC-V eventually compromised and allows both TSO (~ x86) and a weak model (~ Arm). As far as I know, all commercial silicon supports the weak model and I suspect they only support that.