3 ms·
For somebody who knows little about these topics, why was the memory model made the way it was? I assume it's so that the chip would be simpler / more RISCy, an
by sillywalk 3y ago
For somebody who knows little about these topics, why was the memory model made the way it was? I assume it's so that the chip would be simpler / more RISCy, and faster?
- FullyFunctional 3y agoWeaker => more freedom to reorder => issue loads sooner => higher IPC/perf. Really that simple. You can get some of this with speculation and later checking, but that has its own costs and limitation. People feel _very_ strongly about these topics. RISC-V eventually compromised and allows both TSO (~ x86) and a weak model (~ Arm). As far as I know, all commercial silicon supports the weak model and I suspect they only support that.