This sounds like a huge slowdown for linear memory access patterns (max. throughput), which do not fit into L1+L2 cache. I dont see options to prevent L3 cache

This sounds like a huge slowdown for linear memory access patterns (max. throughput), which do not fit into L1+L2 cache. I dont see options to prevent L3 cache time behavior being leaked unless one takes performance cuts for memory access patterns. The only option I do see is something to prevent specific and limited memory as not being allowed into L3 cache altogether. Since you're active and interested in this stuff: What is the state of art on cpusets for flexible task pinning on cores? "Note. There is a minor chance that a task forks during move and its child remains in the root cpuset." is mentioned in the suse docs https://documentation.suse.com/sle-rt/12-SP5/single-html/SLE-RT-shielding/ https://documentation.suse.com/sle-rt/12-SP5/single-html/SLE..., but without any background explanation and I do not understand what stuff breaks on moving pinned Kernel tasks.