2 ms·

I do wonder to what degree we could hard-partition caches, such that speculative prefetches go straight into CPU-specific caches, and doesn't get to go into sha

I do wonder to what degree we could hard-partition caches, such that speculative prefetches go straight into CPU-specific caches, and doesn't get to go into shared caches (e.g. L3) until it stops being speculative. I also wonder to what degree we could partition between user mode and supervisor mode (and provide similar facilities to partition between user-mode and user-mode-sandbox, such as WebAssembly or other JITs), with the same premise. Let the kernel prefetch things but don't let userspace notice the speculated entries.

insanitybit 3y ago
> I do wonder to what degree we could hard-partition caches, such that speculative prefetches go straight into CPU-specific caches, and doesn't get to go into shared caches (e.g. L3) until it stops being speculative. This is already sort of possible. The TLB flushing can take advantage of the PCID to determine, based on the process, whether the cache must be flushed - this provides process level isolation of the TLB. I believe recent CPUs are increasing the size of some PCID related components since it's becoming increasingly important post-kPTI.
matu3ba 3y ago
This sounds like a huge slowdown for linear memory access patterns (max. throughput), which do not fit into L1+L2 cache. I dont see options to prevent L3 cache time behavior being leaked unless one takes performance cuts for memory access patterns. The only option I do see is something to prevent specific and limited memory as not being allowed into L3 cache altogether. Since you're active and interested in this stuff: What is the state of art on cpusets for flexible task pinning on cores? "Note. There is a minor chance that a task forks during move and its child remains in the root cpuset." is mentioned in the suse docs https://documentation.suse.com/sle-rt/12-SP5/single-html/SLE-RT-shielding/ https://documentation.suse.com/sle-rt/12-SP5/single-html/SLE..., but without any background explanation and I do not understand what stuff breaks on moving pinned Kernel tasks.

insanitybit 3y ago

> I do wonder to what degree we could hard-partition caches, such that speculative prefetches go straight into CPU-specific caches, and doesn't get to go into shared caches (e.g. L3) until it stops being speculative. This is already sort of possible. The TLB flushing can take advantage of the PCID to determine, based on the process, whether the cache must be flushed - this provides process level isolation of the TLB. I believe recent CPUs are increasing the size of some PCID related components since it's becoming increasingly important post-kPTI.

matu3ba 3y ago

This sounds like a huge slowdown for linear memory access patterns (max. throughput), which do not fit into L1+L2 cache. I dont see options to prevent L3 cache time behavior being leaked unless one takes performance cuts for memory access patterns. The only option I do see is something to prevent specific and limited memory as not being allowed into L3 cache altogether. Since you're active and interested in this stuff: What is the state of art on cpusets for flexible task pinning on cores? "Note. There is a minor chance that a task forks during move and its child remains in the root cpuset." is mentioned in the suse docs https://documentation.suse.com/sle-rt/12-SP5/single-html/SLE-RT-shielding/ https://documentation.suse.com/sle-rt/12-SP5/single-html/SLE..., but without any background explanation and I do not understand what stuff breaks on moving pinned Kernel tasks.