4 ms·
Also given that Apple (and SPARC) chips have a means to vary the memory model at runtime, I think the way things would go if memory consistency was genuinely bl
by mhh__ 3y ago
Also given that Apple (and SPARC) chips have a means to vary the memory model at runtime, I think the way things would go if memory consistency was genuinely blocking Alpha's progress then they'd change it. It wouldn't be an easy thing to stomach but we have about ten billion flavours of X86 and Arm sub-ISAs floating around today