Yes, it had a weak memory model, which I had to deal with when I was working with a chip subsequently designed by some of the same people so I know its drawback

Yes, it had a weak memory model, which I had to deal with when I was working with a chip subsequently designed by some of the same people so I know its drawbacks better than most. But saying that means it wasn't better is a non sequitur unless your only standard is the strength of the memory model. The weak memory model is, in a way, a continuation of the RISC philosophy: drive up clock speed and IPC by moving complexity from hardware to software. Just like load and branch delays, or (spit) register windows. As time has gone by we've gotten better at hiding those things under a hardware front end, but at the time it was a good choice borne out by the massive success of machines - not just DEC's - based on that philosophy. Yes, it was a pain to deal with, but achieving top-tier performance has always been a pain one way or the other.