Perhaps I'm wrong... but as far as I can see, no RAM technology currently allows variable latency? Ie. the host says "I want data from this address", and th

Perhaps I'm wrong... but as far as I can see, no RAM technology currently allows variable latency? Ie. the host says "I want data from this address", and the RAM can reply 2 clock cycles later with "Here is that data you asked for" or "I'm still getting that data for you, just wait a few more clock cycles please". Such schemes allow the RAM manufacturer to implement error detection/correction/remapping, which would allow them to push their designs far closer to what physics allows. (you can make something much much smaller/faster if you only need it to work 99% of the time, and use a fallback path/mechanism for the remaining 1%)