RVV has masking for everything (masks being stored as packed bits in a vector register), memory gather & scatter, compress (& easily emulatable expand via an in

RVV has masking for everything (masks being stored as packed bits in a vector register), memory gather & scatter, compress (& easily emulatable expand via an instruction that expands 0,1,2,3,… by which you can then shuffle), and in addition to that is scalable (i.e. same code can run on hardware with anything between 128-bit and 65536-bit vector registers; plus something alike "hardware unrolling" where operations can be configured to run over groups of 1/2/4/8 registers; and a vector length option in addition to masking allowing trivially handling the tail of loops with the same body as the main loop, without affecting masking), and is still more orthogonal than AVX-512 (e.g. AVX-512 still only has 8- & 16-bit saturating add/sub, missing 8-bit shifts, whereas RVV has orthogonal everything (even high half of 64-bit product, allowing for two-instruction 64×64→128-bit multiplication)). Granted, it's significantly newer than AVX-512.