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> AVX512 is the most advanced CPU vector instruction set ever made, with huge inspirations from NVidia's PTX or AMD's GCN. Can you explain what makes it the ab

> AVX512 is the most advanced CPU vector instruction set ever made, with huge inspirations from NVidia's PTX or AMD's GCN. Can you explain what makes it the above? I haven't really worked with avx512 before, only up to avx2 and rvv.

dragontamer 3y ago
1. AVX512 allows a 64-bit conditional mask to be used over the 64-bytes (aka a 512-bit operation). Like GPUs (NVidia or AMD) before it, this allows for far simpler implementations of if-statements (or loops) in practice. 2. AVX512 has vgather and vscatter, aka vector-load and vector-store. While no computer accelerates this process, this still simplifies programming and read/writes to memory can be thought of on a per-lane basis. 3. Compress and Expand, new instructions not found in GPU-space, perform the stream-compression operation (and inverse operation). See: https://www.cse.chalmers.se/~uffe/streamcompaction.pdf https://www.cse.chalmers.se/~uffe/streamcompaction.pdf , lots of practical applications here, nice to see just a simple "instruction" that handles this detail. Though GPU programmers can prefix-sum and build this primitive themselves in practice, its a common enough operation that a proper-instruction is likely a good idea. ------------ Just a few tidbits of AVX512 ISA that shows that Intel really knows what they're doing here. #1 can be seen as a 64-bit generalization to the cmov conditional instructions that are in Intel's normal 64-bit instruction set. Except instead of being a "1-bit" compare or 1-bit if-statement, might as well generalize it to a 64-bit operation across 64x8-bit bytes that naturally map into a 512-bit register, right? Its "why" you can just say "if(blahblah)" in CUDA or OpenCL, because under-the-hood, the GPUs are holding onto these 64-bit conditional registers and are turning-off and turning-on lanes to execute. (GPUs don't do if(){A();} else () {B();} like a CPU. GPUs turn on conditional-execution masks per-lane and then execute both A-and-B, though if the lane is "off" then the results are thrown away). It all comes down to S-registers (GCN), opcode-masks (AVX512) or whatnot, its fundamental to "proper" GPU-like SIMD. In any case, AVX512 is still playing catchup to the gpu space, but Intel has shown me (IMO) that they're the CPU-assembly group that has fully understood what makes GPUs tick and why parallelism is possible in CUDA / OpenCL. Maybe they'll leapfrog the GPU guys in the next few years, but I still consider GPUs to be the cream-of-the-crop in terms of assembly-language design for parallel SIMD systems... for today anyway. Then again, NVidia has also shown themselves to be very innovative in this low-level space. And in many ways, its easier to "catch up" (as Intel has done) rather than trailblaze. Still, Intel showing off compression instructions is a good sign, it is true innovation.
- dzaima 3y ago
  RVV has masking for everything (masks being stored as packed bits in a vector register), memory gather & scatter, compress (& easily emulatable expand via an instruction that expands 0,1,2,3,… by which you can then shuffle), and in addition to that is scalable (i.e. same code can run on hardware with anything between 128-bit and 65536-bit vector registers; plus something alike "hardware unrolling" where operations can be configured to run over groups of 1/2/4/8 registers; and a vector length option in addition to masking allowing trivially handling the tail of loops with the same body as the main loop, without affecting masking), and is still more orthogonal than AVX-512 (e.g. AVX-512 still only has 8- & 16-bit saturating add/sub, missing 8-bit shifts, whereas RVV has orthogonal everything (even high half of 64-bit product, allowing for two-instruction 64×64→128-bit multiplication)). Granted, it's significantly newer than AVX-512.

dragontamer 3y ago

1. AVX512 allows a 64-bit conditional mask to be used over the 64-bytes (aka a 512-bit operation). Like GPUs (NVidia or AMD) before it, this allows for far simpler implementations of if-statements (or loops) in practice. 2. AVX512 has vgather and vscatter, aka vector-load and vector-store. While no computer accelerates this process, this still simplifies programming and read/writes to memory can be thought of on a per-lane basis. 3. Compress and Expand, new instructions not found in GPU-space, perform the stream-compression operation (and inverse operation). See: https://www.cse.chalmers.se/~uffe/streamcompaction.pdf https://www.cse.chalmers.se/~uffe/streamcompaction.pdf , lots of practical applications here, nice to see just a simple "instruction" that handles this detail. Though GPU programmers can prefix-sum and build this primitive themselves in practice, its a common enough operation that a proper-instruction is likely a good idea. ------------ Just a few tidbits of AVX512 ISA that shows that Intel really knows what they're doing here. #1 can be seen as a 64-bit generalization to the cmov conditional instructions that are in Intel's normal 64-bit instruction set. Except instead of being a "1-bit" compare or 1-bit if-statement, might as well generalize it to a 64-bit operation across 64x8-bit bytes that naturally map into a 512-bit register, right? Its "why" you can just say "if(blahblah)" in CUDA or OpenCL, because under-the-hood, the GPUs are holding onto these 64-bit conditional registers and are turning-off and turning-on lanes to execute. (GPUs don't do if(){A();} else () {B();} like a CPU. GPUs turn on conditional-execution masks per-lane and then execute both A-and-B, though if the lane is "off" then the results are thrown away). It all comes down to S-registers (GCN), opcode-masks (AVX512) or whatnot, its fundamental to "proper" GPU-like SIMD. In any case, AVX512 is still playing catchup to the gpu space, but Intel has shown me (IMO) that they're the CPU-assembly group that has fully understood what makes GPUs tick and why parallelism is possible in CUDA / OpenCL. Maybe they'll leapfrog the GPU guys in the next few years, but I still consider GPUs to be the cream-of-the-crop in terms of assembly-language design for parallel SIMD systems... for today anyway. Then again, NVidia has also shown themselves to be very innovative in this low-level space. And in many ways, its easier to "catch up" (as Intel has done) rather than trailblaze. Still, Intel showing off compression instructions is a good sign, it is true innovation.

dzaima 3y ago
RVV has masking for everything (masks being stored as packed bits in a vector register), memory gather & scatter, compress (& easily emulatable expand via an instruction that expands 0,1,2,3,… by which you can then shuffle), and in addition to that is scalable (i.e. same code can run on hardware with anything between 128-bit and 65536-bit vector registers; plus something alike "hardware unrolling" where operations can be configured to run over groups of 1/2/4/8 registers; and a vector length option in addition to masking allowing trivially handling the tail of loops with the same body as the main loop, without affecting masking), and is still more orthogonal than AVX-512 (e.g. AVX-512 still only has 8- & 16-bit saturating add/sub, missing 8-bit shifts, whereas RVV has orthogonal everything (even high half of 64-bit product, allowing for two-instruction 64×64→128-bit multiplication)). Granted, it's significantly newer than AVX-512.