3 ms·

Is someone here who understands the nitty bitty details of AVX-512/AVX10 and could tell me what is included which current latest gen AMD processors do not suppo

Is someone here who understands the nitty bitty details of AVX-512/AVX10 and could tell me what is included which current latest gen AMD processors do not support? Because the only thing I can pick out is the 256bit AVX-512 which AFIK recent amd processors do support (including 512bit support) both on their normal cores and their new compacted code. But I don't know much about AVX_ so I'm 100% I missed a bunch of stuff and/or limitations with current AMD code (besides it being double pumped).

zokier 3y ago
Afaik the thing Zen is missing currently is FP16.
jcranmer 3y ago
> Is someone here who understands the nitty bitty details of AVX-512/AVX10 and could tell me what is included which current latest gen AMD processors do not support? Half-precision floating-point for sure.
- adrian_b 3y ago
  As another poster has already mentioned, Zen 4 supports one half-precision FP format, BF16, which was first introduced in Intel Cooper Lake. Sapphire Rapids has added an alternative format FP16, which is not supported by Zen 4, because Zen 4 was launched before Sapphire Rapids.
Falvyu 3y ago
Zen 4 lacks AVX512_FP16 (for 16-bits IEEE floating point operations), AVX512_VP2INTERSECT and also lack the Advanced Matrix eXtension (AMX) set (if you consider that part of AVX512). https://twitter.com/InstLatX64/status/1646471371558461445/ https://twitter.com/InstLatX64/status/1646471371558461445/ It's worth noting that 16-bits floating point operations are still possible on Zen 4, but using Google's BF16.
Zandikar 3y ago
AVX512 subsets *NOT* supported on AMD Zen4 (Epyc 9000, Ryzen 7000): - AVX512ERAVX512PF (Knights Landing) - AVX512 4VNNIW, 4FMAPS (Knights Mill) - VP2INTERSECT (Tiger Lake) - FP16 (Cooper Lake) You can see a table here showing cpu's AVX512 support[0], and wikicpu also has that data in a list [1], along with more detailed info. It's worth noting all data I can find specifically talks about AVX512 support in terms of the architecture (Zen4), not anything specific product families such as ryzen vs epyc implementations. It's possible there is/will be some artificial product segmentation going on (like what Intel did retroactively with Alder Lake to disable AVX512) but I've not seen any mention of it regarding AMD's products. I mention this because Intel has kinda been all over the place with AVX512 implementation, and there's a big difference between Enterprise and Consumer in how they deliver/treat AVX512. AMD obviously is a different company with different practices, but with only 1 generation to go off of it's hard to speculate on a trend, and AVX512 can be an expensive implementation. Point being: It's unfortunately complicated AND subject to change. The "big" one here for ML/DL/AI vs Intel's Sapphire Rapids (and presumably going forward) is FP16 not being supported on AMD. Of course, it's contextual as to whether that's relevant to you though. [0]: https://en.wikipedia.org/wiki/AVX-512?oldformat=true#CPUs_with_AVX-512 https://en.wikipedia.org/wiki/AVX-512?oldformat=true#CPUs_wi... [1]: https://en.wikichip.org/wiki/amd/microarchitectures/zen_4#New_Instructions https://en.wikichip.org/wiki/amd/microarchitectures/zen_4#Ne... My experience is primarily with Intel's implementation of AVX512 in their Xeon products for DL/AI. I can expand on that if interested, but unfortunately haven't had a chance to play with AMD Zen4 yet in that domain, and it's gonna be a while till I can get hands on with a Epyc 9000 probably. EDIT: Fixed typos
- janwas 3y ago
  Minor correction: Cooper Lake added bf16. IEEE half-float fp16 only came in Sapphire Rapids (I am currently adding support for it in Highway).
  - deleted 3y ago
    [deleted]
  - Zandikar 3y ago
    deleted my initial reply as I misread "bf16" in your comment as fp16 and was thoroughly confused. What I Get for commenting before fully awake, sorry lol. And yes, true. That list I just copied from wikichip, didn't think to cross verify what it was conveying in those paranthesis as the question was about AMD not Intel. That said, not sure why they have FP16 attributed to Cooper Lake and not SR. EDIT: Ayy, you can edit wikichip. Fixed it over there (assuming there's not some moderation issue? never submitted anything over there), but too late to edit original HN Comment.

zokier 3y ago

Afaik the thing Zen is missing currently is FP16.

jcranmer 3y ago

> Is someone here who understands the nitty bitty details of AVX-512/AVX10 and could tell me what is included which current latest gen AMD processors do not support? Half-precision floating-point for sure.

adrian_b 3y ago
As another poster has already mentioned, Zen 4 supports one half-precision FP format, BF16, which was first introduced in Intel Cooper Lake. Sapphire Rapids has added an alternative format FP16, which is not supported by Zen 4, because Zen 4 was launched before Sapphire Rapids.

Falvyu 3y ago

Zen 4 lacks AVX512_FP16 (for 16-bits IEEE floating point operations), AVX512_VP2INTERSECT and also lack the Advanced Matrix eXtension (AMX) set (if you consider that part of AVX512). https://twitter.com/InstLatX64/status/1646471371558461445/ https://twitter.com/InstLatX64/status/1646471371558461445/ It's worth noting that 16-bits floating point operations are still possible on Zen 4, but using Google's BF16.

Zandikar 3y ago

AVX512 subsets *NOT* supported on AMD Zen4 (Epyc 9000, Ryzen 7000): - AVX512ERAVX512PF (Knights Landing) - AVX512 4VNNIW, 4FMAPS (Knights Mill) - VP2INTERSECT (Tiger Lake) - FP16 (Cooper Lake) You can see a table here showing cpu's AVX512 support[0], and wikicpu also has that data in a list [1], along with more detailed info. It's worth noting all data I can find specifically talks about AVX512 support in terms of the architecture (Zen4), not anything specific product families such as ryzen vs epyc implementations. It's possible there is/will be some artificial product segmentation going on (like what Intel did retroactively with Alder Lake to disable AVX512) but I've not seen any mention of it regarding AMD's products. I mention this because Intel has kinda been all over the place with AVX512 implementation, and there's a big difference between Enterprise and Consumer in how they deliver/treat AVX512. AMD obviously is a different company with different practices, but with only 1 generation to go off of it's hard to speculate on a trend, and AVX512 can be an expensive implementation. Point being: It's unfortunately complicated AND subject to change. The "big" one here for ML/DL/AI vs Intel's Sapphire Rapids (and presumably going forward) is FP16 not being supported on AMD. Of course, it's contextual as to whether that's relevant to you though. [0]: https://en.wikipedia.org/wiki/AVX-512?oldformat=true#CPUs_with_AVX-512 https://en.wikipedia.org/wiki/AVX-512?oldformat=true#CPUs_wi... [1]: https://en.wikichip.org/wiki/amd/microarchitectures/zen_4#New_Instructions https://en.wikichip.org/wiki/amd/microarchitectures/zen_4#Ne... My experience is primarily with Intel's implementation of AVX512 in their Xeon products for DL/AI. I can expand on that if interested, but unfortunately haven't had a chance to play with AMD Zen4 yet in that domain, and it's gonna be a while till I can get hands on with a Epyc 9000 probably. EDIT: Fixed typos

janwas 3y ago
Minor correction: Cooper Lake added bf16. IEEE half-float fp16 only came in Sapphire Rapids (I am currently adding support for it in Highway).
- deleted 3y ago
  [deleted]
- Zandikar 3y ago
  deleted my initial reply as I misread "bf16" in your comment as fp16 and was thoroughly confused. What I Get for commenting before fully awake, sorry lol. And yes, true. That list I just copied from wikichip, didn't think to cross verify what it was conveying in those paranthesis as the question was about AMD not Intel. That said, not sure why they have FP16 attributed to Cooper Lake and not SR. EDIT: Ayy, you can edit wikichip. Fixed it over there (assuming there's not some moderation issue? never submitted anything over there), but too late to edit original HN Comment.