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from https://cdrdv2.intel.com/v1/dl/getContent/784343 https://cdrdv2.intel.com/v1/dl/getContent/784343 ("The Converged Vector ISA: Intel Advanced Vector Extensi

by canucker2016 3y ago

from https://cdrdv2.intel.com/v1/dl/getContent/784343 https://cdrdv2.intel.com/v1/dl/getContent/784343 ("The Converged Vector ISA: Intel Advanced Vector Extensions 10" Technical Paper PDF) "Intel AVX10 Version 1 will be introduced for early software enablement and supports the subset of all the Intel AVX-512 instruction set available as of future Intel Xeon processors with P-cores, codenamed Granite Rapids, that is forward compatible to Intel AVX10. This version will not include the new 256-bit vector instructions supporting embedded rounding or any of the new instructions and will serve as the transition base version from Intel AVX-512 to Intel AVX10. Intel AVX10 Version 2 will include the 256-bit instruction forms supporting embedded rounding as well as a suite of new Intel AVX10 instructions covering new AI data types and conversions, data movement optimizations, and standards support. All new instructions will be supported at 128-, 256-, and 512-bit vector lengths with limited variances. All Intel AVX10 versions will implement the new versioning enumeration scheme." And who knows when AMD will have time to update Zen ? architecture with these new instructions.

jiggawatts 3y ago
The latest shipping processor is the 4-th generation Intel Xeon "Sapphire Rapids". AVX10 looks like it won't be fully supported until the 6-th generation "Granite Rapids" Xeons, probably in 2025. So AMD has plenty of time to implement the additional instructions, of which there don't appear to be that many. Mostly it's a unification of feature sets and a simplification of the CPU ID flags. Also, Intel is still nerfing the efficiency "E" cores to AVX10-256, so the instruction sets will remain non-uniform in practice for the foreseeable future. Meanwhile, AMD is implementing AVX-512 on all of their CPU cores including in the high-density 128-core AMD EPYC "Bergamo" line, which is a significant differentiator. Intel just cannot resist segmenting a market, even when announcing that they're ending market segmentation!
- brucethemoose2 3y ago
  > So AMD has plenty of time to implement the additional instructions Architectures take years to plan. If AMD is just finding out, I'm not sure they have time. However, one would hope AMD had a little heads up. Its in Intel's and AMD's best interest not to flub the next AVX, with ARM SVE2 (and who knows what else) around the corner.

jiggawatts 3y ago

The latest shipping processor is the 4-th generation Intel Xeon "Sapphire Rapids". AVX10 looks like it won't be fully supported until the 6-th generation "Granite Rapids" Xeons, probably in 2025. So AMD has plenty of time to implement the additional instructions, of which there don't appear to be that many. Mostly it's a unification of feature sets and a simplification of the CPU ID flags. Also, Intel is still nerfing the efficiency "E" cores to AVX10-256, so the instruction sets will remain non-uniform in practice for the foreseeable future. Meanwhile, AMD is implementing AVX-512 on all of their CPU cores including in the high-density 128-core AMD EPYC "Bergamo" line, which is a significant differentiator. Intel just cannot resist segmenting a market, even when announcing that they're ending market segmentation!

brucethemoose2 3y ago
> So AMD has plenty of time to implement the additional instructions Architectures take years to plan. If AMD is just finding out, I'm not sure they have time. However, one would hope AMD had a little heads up. Its in Intel's and AMD's best interest not to flub the next AVX, with ARM SVE2 (and who knows what else) around the corner.