4 ms·
Interesting. More registers and separate destination on instructions is about 40 years overdue, but better late than never. I realized I’ve completely lost tra
by pavlov 3y ago
Interesting. More registers and separate destination on instructions is about 40 years overdue, but better late than never.
I realized I’ve completely lost track of Intel’s architecture extensions reading this:
“They do not change the size and layout of the XSAVE area as they take up the space left behind by the deprecated Intel® MPX registers.”
Apparently MPX was Memory Protection Extensions and the design was so flawed, it was removed entirely soon after introduction.
- deleted 3y ago[deleted]
- theandrewbailey 3y ago> More registers is about 40 years overdue, but better late than never. SSE, AMD64, AVX, and AVX-512 say hi.
- kjs3 3y agoAnd MMX from 1997...so almost 35 of those 40 years ago.
- jlokier 3y agoMMX didn't add new registers. It uses the same FP registers as those present all the way back to the Intel 8087 in 1980. You could say the MMX registers are older than the 32-bit x86 architecture, and therefore older than EAX, EBX, ESP etc.
- kjs3 3y agoNot exactly, especially in the context of this issue. You could use the MMX registers as 'traditional' registers (or at least a scratchpad), not quite like the x87 stack. There are 8 64-bit MMX registers. To avoid having to add new registers, they were made to overlap with the FPU stack register. This means that the MMX instructions and the FPU instructions cannot be used simultaneously. MMX registers are addressed directly, and do not need to be accessed by pushing and popping in the same way as the FPU registers. [1] [1] https://en.wikibooks.org/wiki/X86_Assembly/MMX https://en.wikibooks.org/wiki/X86_Assembly/MMX