4 ms·

RV64GC is mentioned here: https://wiki.debian.org/RISC-V#Hardware_baseline_and_ABI_choice https://wiki.debian.org/RISC-V#Hardware_baseline_and_ABI_cho...

LatticeAnimal 3y ago
Ah, thanks for that! I wonder how they plan to support future extensions like RV64GCV which seems to be gaining traction…
- jrockway 3y ago
  Would it be much different than armhf vs. armel?
  - sanxiyn 3y ago
    Note that NEON is optional for armhf, mainly to support Tegra 2. This was a big deal at the time. See https://wiki.debian.org/ArmHardFloatPort https://wiki.debian.org/ArmHardFloatPort.
- viraptor 3y ago
  Would anything prevent compilers from approaching it like SSE on Intel? Check for feature presence and enable the appropriate path (if using compiler-generated code).
  - cmeacham98 3y ago
    Debian distributes compiled binaries. Thus, they have to either turn processor features on in all their binaries, or off (or distribute two sets of binaries).
    - sanxiyn 3y ago
      Debian does distribute SSE-using binaries (with fallback) on i386 which detects presence of SSE at runtime using CPUID.
    - IntelMiner 3y ago
      You're thinking of optimizing the code for a specific processor. Run-time codepaths that detect CPU features have existed since MMX and SSE
    - pabs3 3y ago
      There are options for runtime instruction selection: https://wiki.debian.org/InstructionSelection https://wiki.debian.org/InstructionSelection
  - sanxiyn 3y ago
    > Check for feature presence That is the hard part. On Intel you can use CPUID, but it is ARM policy to not expose such instructions. You can read /proc/cpuinfo, but that is Linux-specific. Edit: there is a reason for ARM policy: CPUID is a well known virtualization hazard. In fact, KVM immediately traps if you execute CPUID on guest. ARM made a good decision here. Still, it means things can't work exactly like it worked on Intel.
    - erik_seaberg 3y ago
      https://news.ycombinator.com/item?id=18542040 https://news.ycombinator.com/item?id=18542040 talks about registers with a similar purpose.
      - sanxiyn 3y ago
        Only in EL1, which means you can only use them in kernel.
    - viraptor 3y ago
      But specific instructions should be testable anyway, right? Try to execute with an exception handler and you'll know.
      - pm215 3y ago
        On Arm this is generally a bad idea -- there are, or were, some corner cases where the kernel can know that an extension shouldn't be used, but it doesn't have a mechanism for "make the instructions UNDEF". The example I know about is ancient history now -- on the Cortex-A8 I think you could build a kernel without Neon support or perhaps the kernel might find there was a Neon-related erratum, but there was no way to disable Neon to force the UNDEFs. The recommended approach is to use HWCAPs, or else to use the kernel's "emulated ID register accesses" functionality.
    - pm215 3y ago
      The Arm Linux kernel allows you to use some of the "read ID register" instructions from userspace, because it traps them in the kernel and emulates them to present you with a slightly sanitized view of the available hardware: https://www.kernel.org/doc/html/v5.8/arm64/cpu-feature-registers.html https://www.kernel.org/doc/html/v5.8/arm64/cpu-feature-regis... You can also look at the hwcaps (available in the ELF aux vector) -- this is the older mechanism. It's true that there's no cross-OS mechanism to do this, but that's life -- often the OS wants to get in anyway to sanitize the answers (eg so it can tell you "feature X is not present" when it knows about a hardware erratum or the OS was built without feature-X support).

LatticeAnimal 3y ago

Ah, thanks for that! I wonder how they plan to support future extensions like RV64GCV which seems to be gaining traction…

jrockway 3y ago
Would it be much different than armhf vs. armel?
- sanxiyn 3y ago
  Note that NEON is optional for armhf, mainly to support Tegra 2. This was a big deal at the time. See https://wiki.debian.org/ArmHardFloatPort https://wiki.debian.org/ArmHardFloatPort.
viraptor 3y ago
Would anything prevent compilers from approaching it like SSE on Intel? Check for feature presence and enable the appropriate path (if using compiler-generated code).
- cmeacham98 3y ago
  Debian distributes compiled binaries. Thus, they have to either turn processor features on in all their binaries, or off (or distribute two sets of binaries).
  - sanxiyn 3y ago
    Debian does distribute SSE-using binaries (with fallback) on i386 which detects presence of SSE at runtime using CPUID.
  - IntelMiner 3y ago
    You're thinking of optimizing the code for a specific processor. Run-time codepaths that detect CPU features have existed since MMX and SSE
  - pabs3 3y ago
    There are options for runtime instruction selection: https://wiki.debian.org/InstructionSelection https://wiki.debian.org/InstructionSelection
- sanxiyn 3y ago
  > Check for feature presence That is the hard part. On Intel you can use CPUID, but it is ARM policy to not expose such instructions. You can read /proc/cpuinfo, but that is Linux-specific. Edit: there is a reason for ARM policy: CPUID is a well known virtualization hazard. In fact, KVM immediately traps if you execute CPUID on guest. ARM made a good decision here. Still, it means things can't work exactly like it worked on Intel.
  - erik_seaberg 3y ago
    https://news.ycombinator.com/item?id=18542040 https://news.ycombinator.com/item?id=18542040 talks about registers with a similar purpose.
    - sanxiyn 3y ago
      Only in EL1, which means you can only use them in kernel.
  - viraptor 3y ago
    But specific instructions should be testable anyway, right? Try to execute with an exception handler and you'll know.
    - pm215 3y ago
      On Arm this is generally a bad idea -- there are, or were, some corner cases where the kernel can know that an extension shouldn't be used, but it doesn't have a mechanism for "make the instructions UNDEF". The example I know about is ancient history now -- on the Cortex-A8 I think you could build a kernel without Neon support or perhaps the kernel might find there was a Neon-related erratum, but there was no way to disable Neon to force the UNDEFs. The recommended approach is to use HWCAPs, or else to use the kernel's "emulated ID register accesses" functionality.
  - pm215 3y ago
    The Arm Linux kernel allows you to use some of the "read ID register" instructions from userspace, because it traps them in the kernel and emulates them to present you with a slightly sanitized view of the available hardware: https://www.kernel.org/doc/html/v5.8/arm64/cpu-feature-registers.html https://www.kernel.org/doc/html/v5.8/arm64/cpu-feature-regis... You can also look at the hwcaps (available in the ELF aux vector) -- this is the older mechanism. It's true that there's no cross-OS mechanism to do this, but that's life -- often the OS wants to get in anyway to sanitize the answers (eg so it can tell you "feature X is not present" when it knows about a hardware erratum or the OS was built without feature-X support).