3 ms·

> But in your specific example, going from the names, I'm guessing you are meaning Z80, in which case I'd argue that it's 2 registers that are occasionally lump

> But in your specific example, going from the names, I'm guessing you are meaning Z80, in which case I'd argue that it's 2 registers that are occasionally lumped together (e.g. in this case PUSH/POP AF, EX AF,AF') and even with H and L are separate registers where HL is just a specialisation whereby the contents are used in quite a lot of instructions. In what "example"? I never once referenced the z80 architecture here, so half of your post is just going off on some tangent. The only registers I referenced were x86 registers (EAX and RAX). The code example is just a generic example of a union, change the names to ZQ, for all I care.

ralferoo 3y ago
> In what "example"? The source example, that you yourself reference 2 sentences later: > The code example is just a generic example of a union, change the names to ZQ, for all I care. I'm not sure why you're so upset that I thought that might be a reference to Z80, but it's certainly a weird choice for completely random example code otherwise. > The only registers I referenced were x86 registers (EAX and RAX). In your example, you specifically called the structure "Registers" with fields named "AF", "A" and "F". Are you saying that it was completely coincidental that you happened to make a reference to a pair of registers called A and F that can be referenced as a pair using the name AF? Maybe I'm wrong, but the only processors that have an AF register are Z80 and derivatives. In the 8080 and derivatives, the register pairs are known by the name of the MSB register (e.g. "inx d" compared to "inc de" on z80) and the pair of A and F is called PSW. But, even if I was wrong in assuming you meant Z80, and this was a complete coincidence, then what of it? It doesn't change the fundamental point I was making - that these are two independent 8-bit registers that are occasionally exposed as one 16-bit register, compared to the x64 AL,AH,AX,EAX,RAX that are essentially 64-bit registers with smaller views into a subset of the register. The rest of my post wasn't going off on a tangent either - the point I was making is that how the registers are split up and presented to the user isn't very useful, as it's far more interesting to know how many bits of total state there are in a processor, as exposed per-thread, per-core and per-chip.

ralferoo 3y ago

> In what "example"? The source example, that you yourself reference 2 sentences later: > The code example is just a generic example of a union, change the names to ZQ, for all I care. I'm not sure why you're so upset that I thought that might be a reference to Z80, but it's certainly a weird choice for completely random example code otherwise. > The only registers I referenced were x86 registers (EAX and RAX). In your example, you specifically called the structure "Registers" with fields named "AF", "A" and "F". Are you saying that it was completely coincidental that you happened to make a reference to a pair of registers called A and F that can be referenced as a pair using the name AF? Maybe I'm wrong, but the only processors that have an AF register are Z80 and derivatives. In the 8080 and derivatives, the register pairs are known by the name of the MSB register (e.g. "inx d" compared to "inc de" on z80) and the pair of A and F is called PSW. But, even if I was wrong in assuming you meant Z80, and this was a complete coincidence, then what of it? It doesn't change the fundamental point I was making - that these are two independent 8-bit registers that are occasionally exposed as one 16-bit register, compared to the x64 AL,AH,AX,EAX,RAX that are essentially 64-bit registers with smaller views into a subset of the register. The rest of my post wasn't going off on a tangent either - the point I was making is that how the registers are split up and presented to the user isn't very useful, as it's far more interesting to know how many bits of total state there are in a processor, as exposed per-thread, per-core and per-chip.