Ok not affiliated with Cerebras, but generally speaking I believe the idea is that since you're making a big wafer with all your cores the data transport latenc

Ok not affiliated with Cerebras, but generally speaking I believe the idea is that since you're making a big wafer with all your cores the data transport latency for going core to core (much less core to memory/memory bus to gpu memory) is much lower. From first principles there's gains to be had but I suspect "other things" bottleneck performance. Could be wrong though. I would find it hard to believe if absolutely no models were data latency constrained.