I don’t think any of these efficiency claims are true. https://www.uops.info/ https://www.uops.info/ has data for Alder Lake from 2021. For example, some perfor

I don’t think any of these efficiency claims are true. https://www.uops.info/ https://www.uops.info/ has data for Alder Lake from 2021. For example, some performance-critical code I have bottlenecks on FMA instructions like vfmadd132pd. Fast cores: 4 cycles latency, 0.5 cycles throughput, 1 μop Slow cores: 6-10 cycles latency, 1 cycle throughput, 2 μops. Roughly speaking, these numbers mean their fast cores are about 2 times faster for single-threaded arithmetic-heavy code. The numbers for some other arithmetic instructions are even worse for their slow cores. For FP division or square root instructions the gap widens to 4x and 5x the throughput, respectively. As for the AMD, I hope they will do what they recently did in their Zen4c microarchitecture in the newly launched server chips: reduce clocks speeds, reduce L3 cache, but don’t cripple the actual cores.