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> Not that having a ton of E-cores isn't cool Personally, I don’t find that cool, and I think I will stay with AMD CPU for my next desktop. I want all cores to

> Not that having a ton of E-cores isn't cool Personally, I don’t find that cool, and I think I will stay with AMD CPU for my next desktop. I want all cores to be fast, and I have enough parallelizable work for them. Also I’d like to get AVX-512: Intel doesn’t support that in their reasonably-priced consumer targeted CPUs. > I haven't seen an explanation of whether that's really the equivalent of 4 DDR4 memory channels. For throughput, it could be the case. DDR4-3200 has theoretical peak 25 GB/sec/channel, for DDR5-8000 62.5 GB/sec/channel.

FirmwareBurner 3y ago
> I want all cores to be fast E-cores aren't slow just because they're not called "performance" cores, they're just more efficient at lower clock speeds and more in numbers, optimized specifically for multi-threaded tasks you said you need. P-cores are great mostly for single thread tasks that bank on high clock speeds, that's why the CPU has so few of them, as it seeks to cram in as many E-cores as possible. AMD is also going the big.LITTLE route with the next Ryzen generation.
- Const-me 3y ago
  I don’t think any of these efficiency claims are true. https://www.uops.info/ https://www.uops.info/ has data for Alder Lake from 2021. For example, some performance-critical code I have bottlenecks on FMA instructions like vfmadd132pd. Fast cores: 4 cycles latency, 0.5 cycles throughput, 1 μop Slow cores: 6-10 cycles latency, 1 cycle throughput, 2 μops. Roughly speaking, these numbers mean their fast cores are about 2 times faster for single-threaded arithmetic-heavy code. The numbers for some other arithmetic instructions are even worse for their slow cores. For FP division or square root instructions the gap widens to 4x and 5x the throughput, respectively. As for the AMD, I hope they will do what they recently did in their Zen4c microarchitecture in the newly launched server chips: reduce clocks speeds, reduce L3 cache, but don’t cripple the actual cores.
  - roboror 3y ago
    It's a common misconception, they are die area efficient.
- bick_nyers 3y ago
  I'm pretty sure Lisa Su just said recently that AMD is not going big.LITTLE
  - FirmwareBurner 3y ago
    Leaked roadmaps of AMD say otherwise, at least for consumer parts. Zen 5 is rumored be go big.LITTLE.
    - bick_nyers 3y ago
      Looks like it wasn't Lisa Su's comments I was remembering: https://www.techpowerup.com/review/amd-ryzen-interview-ai-zen-4-strategy/4.html https://www.techpowerup.com/review/amd-ryzen-interview-ai-ze... TL;DR: They have been experimenting with big.LITTLE internally and likely aren't targeting desktop first, if at all. The AMD VP seems more concerned with power constrained environments such as mobile/laptop for a big.LITTLE product.
LargeTomato 3y ago
>I want all cores to be fast, and I have enough parallelizable work for them. To each their own, but I just want to browse Lemmy and play RimWorld. My PC is from 2016 and it works great.

FirmwareBurner 3y ago

> I want all cores to be fast E-cores aren't slow just because they're not called "performance" cores, they're just more efficient at lower clock speeds and more in numbers, optimized specifically for multi-threaded tasks you said you need. P-cores are great mostly for single thread tasks that bank on high clock speeds, that's why the CPU has so few of them, as it seeks to cram in as many E-cores as possible. AMD is also going the big.LITTLE route with the next Ryzen generation.

Const-me 3y ago
I don’t think any of these efficiency claims are true. https://www.uops.info/ https://www.uops.info/ has data for Alder Lake from 2021. For example, some performance-critical code I have bottlenecks on FMA instructions like vfmadd132pd. Fast cores: 4 cycles latency, 0.5 cycles throughput, 1 μop Slow cores: 6-10 cycles latency, 1 cycle throughput, 2 μops. Roughly speaking, these numbers mean their fast cores are about 2 times faster for single-threaded arithmetic-heavy code. The numbers for some other arithmetic instructions are even worse for their slow cores. For FP division or square root instructions the gap widens to 4x and 5x the throughput, respectively. As for the AMD, I hope they will do what they recently did in their Zen4c microarchitecture in the newly launched server chips: reduce clocks speeds, reduce L3 cache, but don’t cripple the actual cores.
- roboror 3y ago
  It's a common misconception, they are die area efficient.
bick_nyers 3y ago
I'm pretty sure Lisa Su just said recently that AMD is not going big.LITTLE
- FirmwareBurner 3y ago
  Leaked roadmaps of AMD say otherwise, at least for consumer parts. Zen 5 is rumored be go big.LITTLE.
  - bick_nyers 3y ago
    Looks like it wasn't Lisa Su's comments I was remembering: https://www.techpowerup.com/review/amd-ryzen-interview-ai-zen-4-strategy/4.html https://www.techpowerup.com/review/amd-ryzen-interview-ai-ze... TL;DR: They have been experimenting with big.LITTLE internally and likely aren't targeting desktop first, if at all. The AMD VP seems more concerned with power constrained environments such as mobile/laptop for a big.LITTLE product.

LargeTomato 3y ago

>I want all cores to be fast, and I have enough parallelizable work for them. To each their own, but I just want to browse Lemmy and play RimWorld. My PC is from 2016 and it works great.