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The main magic I do for RISC CPUs is allowing a write callback binding to the registers (overloading operator=) This allows us to handle pipeline invalidation o
by byuu 15y ago
The main magic I do for RISC CPUs is allowing a write callback binding to the registers (overloading operator=) This allows us to handle pipeline invalidation on writes to the PC register, without having to special case the hell out of every single instruction that can modify it.
- simcop2387 15y agoAh seems my memory was bad there. I must have had it confused with another emulator, however that sounds while it wouldn't be trivial to rewrite those sections it shouldn't be very difficult to do so either, just very very tedious. I think other than that there could only be a licensing issue, and I seem to recall that bsnes had a fairly liberal license that shouldn't run into any problems. Though obviously you'll know better than me byuu :) In that case it's all about time and who has it that'll determine when/if it'll happen
- grantg 15y agoKeep up the good work Byuu.