Xilinx's Vertex 7 FPGA uses a stacked design for the interconnects. The FPGA logic is all 28nm, but sitting under it is a completely passive 65nm interconnect l

Xilinx's Vertex 7 FPGA uses a stacked design for the interconnects. The FPGA logic is all 28nm, but sitting under it is a completely passive 65nm interconnect layer. http://www.xilinx.com/products/technology/stacked-silicon-interconnect/index.htm http://www.xilinx.com/products/technology/stacked-silicon-in...